Nonvolatile ferroelectric memory device and method for detecting weak cell using the same

ABSTRACT

A nonvolatile ferroelectric memory device and a method for detecting a weak cell using the same are provided. The nonvolatile ferroelectric memory device includes: a nonvolatile ferroelectric memory cell driver including a top cell array and a bottom cell array, a sensing amplifier formed between the top and bottom cell arrays for sensing the top and bottom cell arrays, and a wordline driver for driving a wordline of the top and bottom cell arrays; an X-decoder for selectively outputting a wordline decoding signal to the wordline driver; and a pulse width generating unit for varying a width of a restore pulse PW1 and outputting the varied width to the wordline driver to detect a weak cell of the top and bottom cell arrays.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor memory device, and moreparticularly, to a nonvolatile ferroelectric memory device and methodfor detecting a weak cell using the same.

2. Background of the Related Art

Generally, a nonvolatile ferroelectric memory, i.e., a ferroelectricrandom access memory (FRAM) has a data processing speed equal to adynamic random access memory (DRAM) and retains data even in power off.For this reason, the nonvolatile ferroelectric memory has received muchattention as a next generation memory device.

The FRAM and DRAM are memory devices with similar structures, but theFRAM includes a ferroelectric capacitor having a high residualpolarization characteristic. The residual polarization characteristicpermits data to be maintained even if an electric field is removed.

FIG. 1 shows hysteresis loop of a general ferroelectric. As shown inFIG. 1, even if polarization induced by the electric field has theelectric field removed, data is maintained at a certain amount (i.e., dand a states) without being erased due to the presence of residualpolarization (or spontaneous polarization). A nonvolatile ferroelectricmemory cell is used as a memory device by corresponding the d and astates to 1 and 0, respectively.

A related art nonvolatile ferroelectric memory device will now bedescribed. FIG. 2 shows unit cell of a related art nonvolatileferroelectric memory.

As shown in FIG. 2, the related art nonvolatile ferroelectric memoryincludes a bitline B/L formed in one direction, a wordline W/L formed tocross the bitline, a plate line P/L spaced apart from the wordline inthe same direction as the wordline, a transistor T1 with a gateconnected with the wordline and a source connected with the bitline, anda ferroelectric capacitor FC1. A first terminal of the ferroelectriccapacitor FC1 is connected with a drain of the transistor T1 and asecond terminal is connected with the plate line P/L.

In the related art nonvolatile ferroelectric memory including unitcells, weak cells occur due to defect of the ferroelectric capacitor ofeach unit cell.

To detect such weak cells, an offset sensing amplifying circuit shown inFIG. 3 is typically used. That is, a sensing margin is varied by addingan offset voltage to a sensing voltage of a bit line.

A method for detecting weak cells using the related art nonvolatileferroelectric memory will be described with reference to theaccompanying drawings.

FIG. 3 is a diagram of an offset control circuit of a related artsensing amplifier, and FIG. 4 is a graph showing the variation of anoffset voltage according to a bitline voltage during a reading mode ofthe cell.

As shown in FIG. 3, the offset control circuit of the related artsensing amplifier includes a bitline, a bitline bar, a first inverter,and a second inverter. The first inverter inverts a bitline signalbetween the bitline and the bitline bar, and the second inverter invertsa bitline bar signal and outputs the inverted signal to the bitline.

A first switching transistor and a first offset capacitor are providedbetween the bitline and a driver while a second switching transistor anda second offset capacitor are provided between the bitline bar and thedriver.

At this time, the first switching transistor transmits the bitlinesignal to the driver through the offset capacitor while the secondswitching transistor transmits the bitline bar signal to the driverthrough the offset capacitor.

The related art method for detecting weak cells is performed using theoffset control circuit shown in FIG. 3. In this method, the sensingmargin is varied by adding the offset voltage to the bitline sensingvoltage.

In other words, addition of an offset to a normal bitline level breaksloading balance of the bitline, and an operational margin of a sensingamplifier is reduced during sensing operation. Thus, weak cells aredetected.

FIG. 4 is a graph showing variation of an offset voltage according to abitline voltage during related art reading mode. Referring to FIG. 4, ifthe bitline voltage is small during the reading mode, the offset voltageapplied to the bitline becomes small. If the bitline voltage is great,the offset voltage becomes grater.

The related art method for detecting weak cells using the related artnonvolatile ferroelectric memory has several problems.

Since a separate offset capacitor is required to detect the weak cells,the process becomes complicated. If the process conditions are varied, anormal bitline level is varied. This may cause an error in detecting theweak cells.

SUMMARY OF THE INVENTION

An object of the invention is to solve at least the above problemsand/or disadvantages and to provide at least the advantages describedhereinafter.

Another object of the present invention is to provide a nonvolatileferroelectric memory device and method for detecting a weak cell usingthe same in which a separate test mode is not required, and a weak cellis easily detected and eliminated even if process conditions are varied.

To achieve at least these objects and other advantages in a whole or inpart and in accordance with the purpose of the present invention, as embodied and broadly described, a nonvolatile ferroelectric memory deviceaccording to the present invention includes: a nonvolatile ferroelectricmemory cell driver including a top cell array and a bottom cell array, asensing amplifier formed between the top and bottom cell arrays, forsensing the top and bottom cell arrays, and a wordline driver fordriving a wordline of the top and bottom cell arrays; an X-decoder forselectively outputting a wordline decoding signal to the wordlinedriver; and a pulse width generating unit for varying a width of arestore pulse PW1 and outputting the varied width to the wordline driverto detect a weak cell of the top and bottom cell arrays.

To further achieve the above objects in a whole or in part according tothe present invention, a method for detecting a weak cell using anonvolatile ferroelectric memory device including a nonvolatileferroelectric memory cell driver having a top cell array and a bottomcell array, a sensing amplifier for sensing the top and bottom cellarrays, and a wordline driver for driving a wordline of the top andbottom cell arrays, includes the steps of:

selectively outputting a wordline decoding signal to the wordlinedriver; varying a width of a restore pulse PW1 and outputting therestored pulse having a varied width to the wordline driver to detect aweak cell of the upper and lower cell arrays; controlling data(chargeamount) to be stored in a memory cell of each cell array to correspondto the size of the output restore pulse PW1 and outputting bitlinesensing levels varied to correspond to the size of the restore pulse;and sensing a memory cell that reaches a minimum sensing level among thevaried bitline sensing levels to determine a weak cell.

These and other objects of the present application will become morereadily apparent from the detailed description given hereinafter.However, it should be understood that the detailed description andspecific examples, while indicating preferred embodiments of theinvention, are given by way of illustration only, since various changesand modification within the spirit and scope of the invention willbecome apparent to those skilled in the art from this detaileddescription.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will be described in detail with reference to thefollowing drawings in which like reference numerals refer to likeelements wherein:

FIG. 1 shows hysteresis loop of a general ferroelectric;

FIG. 2 is a schematic view of a unit cell of a related art nonvolatileferroelectric memory;

FIG. 3 is a diagram of an offset control circuit of a related artsensing amplifier;

FIG. 4 is a graph showing variation of an offset voltage according to abitline voltage during related art reading operation;

FIG. 5 is a schematic view of a nonvolatile ferroelectric memory deviceaccording to an embodiment of the present invention;

FIG. 6 is a schematic view of a memory cell array according to thenonvolatile ferroelectric memory device of FIG. 5;

FIG. 7 is a circuit diagram of a unit main cell of FIG. 6;

FIG. 8 is a circuit diagram of a reference cell of FIG. 6;

FIG. 9 is a timing chart showing the operation of a write mode accordingto an embodiment of the nonvolatile ferroelectric memory device of thepresent invention;

FIG. 10 is a timing chart showing the operation of a read mode accordingto an embodiment of the nonvolatile ferroelectric memory device of thepresent invention;

FIG. 11 is a circuit diagram of the pulse width variable controller inFIG. 5;

FIG. 12 is a circuit diagram of the first switching signal generator inFIG. 5;

FIG. 13 is a circuit diagram of the second switching signal generator inFIG. 5;

FIG. 14 is a graph showing dependancy of memory charges according to thesize of the pulse width PW1;

FIGS. 15(a)-15(c) show various examples of the pulse width PW1;

FIG. 16 shows dependancy of a voltage induced to a bitline B/L accordingto variation of the pulse width PW1 in FIG. 15;

FIG. 17 is a schematic view illustrating the operation of a high voltagesensing synchronizing circuit in FIG. 5; and

FIGS. 18(a)-18(d) illustrate the pulse widths PW1 according to signalwaveforms SWC1 and SWC2 of FIG. 17.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Reference will now be made in detail to the preferred embodiments of thepresent invention, examples of which are illustrated in the accompanyingdrawings.

In the present invention, it is intended that a weak cell is eliminatedin advance to ensure reliability of a nonvolatile ferroelectric memorychip. That is, an operational pulse width of a cell is varied to controldata to be stored in the cell, so that a bitline sensing level isvaried. A sensing input voltage of a sensing amplifier is varied toallow a weak cell to reach a minimum sensing level, thereby eliminatingthe weak cell.

A nonvolatile ferroelectric memory device and method for detecting aweak cell using the same will now be described with reference to theaccompanying drawings.

First, as shown in FIG. 5, the nonvolatile ferroelectric memory deviceof the present invention includes a memory cell array 50, a wordlinedriver 57, an X-decoder 51 for driving the wordline driver 57, and apulse generator 56 for detecting a weak cell of the memory cell array50.

The memory cell array 50, as shown in FIGS. 5 and 6, includes aplurality of sub cell arrays. A sensing amplifier S/A 120 is formedbetween adjacent top and bottom sub cell arrays sub_T and sub_B.

As shown in FIG. 6, each of the sub cell arrays includes bitlinesTop_B/L and Bot_B/L, a plurality of main cells MC connected to thebitlines Top_B/L and Bot_B/L, a reference cell RC connected to thebitlines Top_B/L and Bot_B/L, and a column selector CS.

The reference cell RC within the sub cell array sub_T formed in a topportion of the sensing amplifier S/A is simultaneously accessed when themain cell MC within the sub cell array sub_B is accessed.

On the other hand, the reference cell RC within the sub cell array sub_Bformed in a bottom portion of the sensing amplifier S/A issimultaneously accessed when the main cell MC within the sub cell arraysub_T is accessed.

The column selector CS selectively activates a corresponding columnbitline using a Y(column) address.

If the column selector CS is in high level, the corresponding columnbitline is connected to a data bus, so as to enable data transmission.

The main cell MC is constructed as shown in FIG. 7. As shown, a bitlineB/L is formed in one direction, and a wordline W/L is formed to crossthe bitline B/L. A plate line P/L is spaced apart from the wordline W/Lin the same direction as the wordline W/L. A transistor T, with a gateconnected with the wordline W/L and a source connected with the bitlineB/L, is formed. A ferroelectric capacitor FC is formed in such a mannerthat its first terminal is connected with a drain of the transistor Tand its second terminal is connected with the plate line P/L.

FIG. 8 is a detailed schematic view of the reference cell RC of thenonvolatile ferroelectric memory device according to an embodiment ofthe present invention. As shown in FIG. 8, the reference cell RC of thenonvolatile ferroelectric memory device includes a bitline B/L formed inone direction, a reference wordline REF_W/L formed across the bitline, aswitching block 81, a level initiating block 82, and a plurality offerroelectric capacitors FC1, FC2, FC3, FC4, . . . , FCn. The switchingblock 81 is controlled by a signal of the reference wordline REF_W/L toselectively transmit a reference voltage stored in the ferroelectriccapacitors to the bitline B/L. The level initiating block 82 selectivelyinitiates a level of an input terminal of the switching block 81connected to the ferroelectric capacitors. The ferroelectric capacitorsare connected to the input terminal of the switching block 81 inparallel.

The switching block 81 includes an NMOS transistor (hereinafter, “firsttransistor”) T1 with a gate connected to the reference wordline REF_W/L,a drain connected to the bitline B/L, and a source connected to astorage node SN.

The level initiating block 82 is controlled by a reference cellequalizer control signal REF_EQ, which is a control signal forinitiating the storage node SN of the reference cell RC. Also, the levelinitiating block 82 includes an NMOS transistor (hereinafter, “secondtransistor”) T2 connected between the source of the first transistor T1and a ground terminal Vss.

The ferroelectric capacitors FC1, FC2, FC3, FC4, . . . , FCn include afirst electrode, a second electrode, and a ferroelectric material formedbetween first and second electrodes. The first electrode of eachferroelectric capacitor is connected to the source of the firsttransistor T1, and its second electrode is connected to the referenceplate line REF_P/L.

The number of the ferroelectric capacitors FC1, FC2, FC3, FC4, . . . ,FCn is determined depending on the desired capacitor size of thereference cell. That is, the number of the ferroelectric capacitors canfreely be adjusted depending on the capacitor size of the referencecell.

The storage node SN is connected with first terminals of theferroelectric capacitors FC1, FC2, FC3, FC4, . . . , FCn in parallel.

The reference cell equalizer control signal REF_EQ initiates the storagenode SN to a ground voltage level. Namely, if the reference cellequalizer control signal REF_EQ is in high level, the second transistorT2 is turned on so that the storage node SN is maintained at a groundvoltage level.

The operation of the aforementioned reference cell will now bedescribed. Qs and Qns of the hysteresis loop in FIG. 1 denote switchingcharges of the ferroelectric capacitor and non-switching charges of theferroelectric capacitor, respectively. The reference cell of the presentinvention is based on Qns. That is to say, the reference wordlineREF_W/L within the operation cycle is transited to high level togetherwith the reference plate line REF_P/L. Accordingly, charges equivalentto the size of Qns of the ferroelectric capacitor are supplied to thebitline B/L.

Then, the reference wordline REF_W/L is transited to low level beforethe sensing amplifier is operated, so that the reference cell is notaffected by a voltage of the bitline B/L.

Meanwhile, the reference plate line REF_P/L is maintained at high level,and is transited to low level when the reference wordline REF_W/L issufficiently stabilized.

As described above, since non-switching charges Qns are used, a separaterestoring operation is not required during a precharge period.Accordingly, high level is not required any longer in the referencewordline REF_W/L.

Since the reference level is affected by an initial level of the storagenode SN, the second transistor T2 of FIG. 8 is used to stabilize thestorage node SN, and the reference equalizer control signal REF_EQ isused to initiate the storage node SN to the ground voltage level.Therefore, since the initial level of the storage node SN is maintainedat the ground voltage level, the reference level can be stabilized.

Reading and writing operations of the nonvolatile ferroelectric memorydevice according to the present invention will now be described.

FIG. 9 is a timing chart showing the operation of a write mode accordingto the nonvolatile ferroelectric memory device of the present invention,and FIG. 10 is a timing chart showing the operation of a read modeaccording to the nonvolatile ferroelectric memory device of the presentinvention.

The write mode and read mode differ from each other in the direction ofthe transmission of data. Referring to FIG. 9, external data is forciblyinput to the bitline B/L through a data input pad when the writingoperation is performed by a write enable signal WEBpad. During the readoperation, referring to FIG. 10, data amplified by the sensing amplifieris transmitted to an external data input/output pad.

With reference to the waveforms of FIG. 9, the data writing operationwill be described.

One cycle is completed in such a manner that an external chip enablesignal CSBpad is transited to low level to start an active period andthen a precharge period advances.

If an active period of a chip starts at the beginning of period A, thenaddress decoding starts during a period A. A corresponding wordline W/L,a corresponding plate line P/L, a corresponding reference wordlineREF_W/L, and a corresponding reference plate line REF_P/L are activatedat high levels as various control signals are activated.

During period B, the wordline W/L and the reference wordline REF_W/L aremaintained at a high level, so that the data of the main cell MC and thedata of the reference cell RC are respectively transmitted to theirbitlines B/L. Also, the main cell has a logic value of “0” and isamplified in period C.

For reference, the bitline B/L to which the data of the main cell MC istransmitted is not the same as the bitline B/L to which the data of thereference cell RC is transmitted. Namely, as described above, among subcell arrays, the main cell MC within the sub cell array at the topportion of the sensing amplifier is operated together with the referencecell within the sub cell array at the bottom portion of the sensingamplifier. Accordingly, the data of the main cell is transmitted to thebitline within the sub cell array at the top portion while the data ofthe reference cell is transmitted to the bitline within the sub cellarray at the bottom portion.

When the data of the main cell and the data of the reference cell aresufficiently transmitted to their corresponding bitline, the wordlineW/L and the reference wordline REF_W/L are transited to low level sothat the bitline B/L is separated from the cell.

Therefore, bitline loading due to the difference of the capacitor sizebetween the main cell and the reference cell can be removed. Thisimproves a sensing margin of the sensing amplifier.

When the wordline W/L and the reference wordline REF_W/L are transitedto low level, a sensing amplifier enable signal SEN of the sensingamplifier is activated at high level during a period C. Thus, the dataof the bitline is (referring to the bitline of the MC and the bitline ofthe reference cell RC) is amplified.

At this time, the plate line P/L and the reference wordline REF_W/L aremaintained at high level and then transited low level when a period Dstarts. A high pulse of column selector CS is received in period D sothat the external data of the bitline B/L is sent to the data bus DB.

In period E, W/L is high while P/L remains low, so that data having alogic value of “1” is written in the main cell MC.

Finally, it is noted that the plate line P/L and reference plate lineREF_P/L are not transited when the wordline W/L and the referencewordline REF_W/L are transited. Accordingly, interference noise that mayoccur due to simultaneous transition of the plate line P/L and thewordline W/L or the reference wordline REF_W/L and the reference plateline REF_P/L can be avoided.

Afterwards, the amplification operation of the sensing amplifierproceeds to a stable mode.

The operation of the read mode will now be described with reference FIG.10.

In the read mode, the data of the bitline is transmitted to the databus. The read mode operations is implemented with timing such as thetiming of the write mode. Data of the cell in the period B has a logicvalue of “0” and is amplified in period C. Column selector CS isactivated to a high level period D . At this time, the data of the maincell MC is output to the sensing amplifier S/A and the previous datahaving a logic value of “1” is restored in the main cell MC duringperiod E.

In other words, a precharge period starts if the external chip enablesignal CSBpad is transited to high level. Then, the wordline W/L is onlytransited from low level to high level during a period E. At this time,since the sensing amplifier enable signal SEN is continuously maintainedat high level to activate the sensing amplifier, the bitline B/Lcontinuously maintains amplified data or reprogrammed data.

Accordingly, the data of the main cell having a logic value “1”,destroyed during the period B, is restored. This is called a restoringoperation.

If the restoring operation is completed, the bitline B/L and the storagenode SN of the reference cell RC are initiated at the ground voltagelevel during the period F, to start the next cycle.

Next, the pulse generator 56 for detecting a weak cell using a variablecharge amount stored in the ferroelectric capacitor of the main cell MCdepending on the size of the restore pulse width PW1 during the readmode will be described.

As shown in FIG. 5, the pulse generator 56 includes a switching signalgenerating unit 54, which includes a first switching signal generator 52and a second switching signal generator 53, and a pulse width variablecontroller 55 for selectively receiving signals SWC1 and SWC2 outputfrom the first and second switching signal generators 52 and 53 and forvarying the pulse PW1.

As shown in FIG. 11, the pulse width variable controller 55 includesfirst, second and third PMOS transistors DP1, DP2 and DP3 and a firstNMOS transistor NM1 connected in series. An input signal INPUT is inputto the gates of the first-third PMOS transistors DP1-DP3 and the firstNMOS transistor NM1. The first, second and third PMOS transistors DP1,DP2 and DP3 and the first NMOS transistor NM1 are connected in seriesbetween a power source voltage terminal VCC and a ground voltageterminal VSS. Fourth and fifth PMOS transistors SP1 and SP2 arerespectively connected with the first PMOS transistor DP1 and the secondPMOS transistor DP2 in parallel, and are driven by the first and secondswitching signals SWC1 and SWC2 for varying the pulse width. The pulsewidth variable controller 55 further includes a first inverter INV1 forinverting a signal of a common node of the third PMOS transistor DP3 andthe first NMOS transistor NM1 to output the restore pulse PW1.

The width of the restore pulse PW1 output from the pulse width variablecontroller 55 is determined depending on the first and second switchingsignals SWC1 and SWC2.

The first and second switching signal generators 52 and 53 forgenerating the first and second switching signals SWC1 and SWC2 will nowbe described.

FIG. 12 is a circuit diagram of the first switching signal generator ofFIG. 5, and FIG. 13 is a circuit diagram of the second switching signalgenerator of FIG. 5.

First, as shown in FIG. 12, the first switching signal generator 52includes a system power voltage sensitive divider 121, a signalsynchronizing unit 122, a level maintaining unit 123, a currentsupplying unit 124, a control unit 125, and a high voltage determiningunit 126.

The system power voltage sensitive divider 121 includes a plurality ofNMOS transistors Tn1-Tnn connected in series. Each of the NMOStransistors Tn1˜Tnn has a gate to which the power source voltage VCC isapplied. The system power voltage sensitive divider 121 supplies thesystem power at a constant ratio to output a power voltage variationvalue to a first output terminal out1 (the node between second and thirdNMOS transistors Tn2 and Tn3).

The signal synchronizing unit 122 synchronizes an output variation ofthe system power voltage sensitive divider 121 with a chip enable signalCE and the output first switching signal SWC1. The signal synchronizingunit 122 includes two NMOS transistors T1 and T2 connected in parallelbetween a source terminal of the last NMOS transistor Tnn of the divider121 and the ground voltage terminal VSS. The chip enable signal CE andthe first switching signal SWC1 are respectively connected to the firstand second NMOS transistors T1 and T2, and pull the first outputterminal out1 to ground when either of the chip enable signal CE or thefirst switching signal SWC1 is high.

As shown in FIG. 17, the divider 121 outputs a lower output signal tothe first output terminal out1 in a state that the external chip enablesignal CSBpad is activated and the divider 121 outputs a higher outputsignal to the first output terminal out1 in a state that the externalchip enable signal CSBpad is deactivated.

The level maintaining unit 123 includes a PMOS transistor T4, connectedbetween the power source voltage terminal VCC and the drain terminal ofan NMOS transistor T3, and an inverter INV2 for inverting a signal of asource terminal of the PMOS transistor T4 (referred to as the secondoutput terminal out2) and inputting it to the gate terminal of the PMOStransistor T4.

The level maintaining unit 123 maintains a high level only when thesecond output terminal out2 of a drain terminal of the NMOS transistorT3, switched depending on the output signal of the first output terminalout1 of the system power sensitive divider 121, is in the high level(i.e., first output terminal out1 is low and the NMOS transistor T3 doesnot pull the second output terminal to VCC). The level maintaining unit123 is not operated if the output signal of the second output terminalout2 is in low level.

The current supplying unit 124 includes a PMOS transistor T5 connectedbetween the power source voltage terminal VCC and the second outputterminal out2. The current supplying unit 124 acts to supply current tothe drain terminal of the NMOS transistor T3, and maintains the outputsignal of the second output terminal out2 at high level in a normalvoltage state.

The control unit 125 acts to control the current supplying unit 124, andincludes an inverter INV3 for inverting a signal of the source terminalof the PMOS transistor T4 and a NAND gate NI for performing logic ANDoperation of the chip enable signal CE and the signal of the inverterINV3 and inverting the resultant value. The output of the NAND gate N1serves as the fourth output terminal out4, which is connected to thegate of the PMOS transistor T5 and controls the operation thereof.

An output signal of a fourth output terminal out4, the output of theNAND gate N1, will be at a low level when the output signal of thesecond output terminal out2 is at a low level and the chip enable signalCE is at a high level. This activates the PMOS transistor T5 of thecurrent supplying unit 124 to supply current to the second outputterminal out2.

The output signal of the second output terminal out2 can be sufficientlymaintained in a normal voltage state even when current is supplied tothe second output terminal out2. When in a low voltage region, theoutput signal of the second output terminal out2 is boosted at highlevel to output high data to the third output terminal out3.Accordingly, a high voltage state is detected when the switching signalSWC1 is in low level.

The high voltage determining unit 126 detects a power source voltage todetermine a high voltage and a normal voltage. The output signal of theoutput terminal out2 is in high level in a normal voltage region whilethe output signal of the output terminal out2 is in low level in a highvoltage region. The normal voltage region exists when SP1 and SP2 areturned off and as shown in FIG. 17, and is when SWC1 and SWC2 becomehigh. The high voltage regions occurs when either SP1 or SP2 is turnedon as either SWC1 or SWC2 becomes low, as shown in FIG. 17.

The high voltage determining unit 126 includes an NMOS transistor T3 andtwo inverters INV4 and INV5. The NMOS transistor T3 is connected betweenthe source terminal of the PMOS transistor T4 and the ground voltageterminal VSS, and its level is determined in response to variation ofthe output signal of the first output terminal out1 of the system powersensitive divider 121. The two inverters INV4 and INV5 are seriallyconnected with each other to delay the signal of the drain terminal ofthe NMOS transistor T3.

As shown in FIG. 13, the switching signal generator 53 has the samestructure as the first switching signal generator 52 except that thedivider 121 has been replaced with a system power voltage divider 131.The system power voltage divider 131 is similar to the system powervoltage divider 121 and includes a plurality of NMOS transistorsTn1-Tnn. However, the first and second NMOS transitors Tn1 and Tn2 areconnected to the power source voltage terminal Vcc by a diode connectorwhile the other NMOS transistors Tn3-Tnn are connected to one another inseries having a gate to which the power source voltage is applied.

The aforementioned switching signal generators 52 and 53 control thefourth and fifth PMOS transistors SP1 and SP2 (see FIG. 11) of the pulsewidth variable controller 55 so as to generate the first and secondswitching signals SWC1 and SWC2 for controlling the pulse width PW1.

As shown in FIGS. 11 and 17, when the system power voltage is normal,switching signals SWC1 and SWC2 are in high level so the fourth andfifth PMOS transistors SP1 and SP2 are turned off. When the system poweris high, switching signals SWC1 and SWC2 are in a low level so that SP1and SP2 are turned on. Also, the system power voltage at the point thatswitching signal SWC1 is transmitted to a low level is lower than thesystem power voltage when switching signal SWC2 is transmitted to lowlevel. As a result, when switching signal SWC1 is in a low level andswitching signal SWC2 is in a higher level, SP1 is on while SP2 is off.

The operation of the pulse width variable controller 55, based on theswitching signals SWC1 and SWC2 output through the aforementioned firstand second switching signal generators 52 and 53, will now be described.

As shown in FIGS. 11, 17 and 18 a-d, when a waveform of the input signalINPUT is as shown in FIG. 18d and the first and second switching signalsSWC1 and SWC2 are all in low level as shown in FIG. 17, then the voltageVCC is transferred by the third and fourth PMOS transistors SP1 and SP2and is only delayed by the third PMOS transistor DP3 because the fourthand fifth PMOS transistors SP1 and SP2 are turned on. The pulse widthPW1 is as shown in FIG. 18b.

In FIG. 18a, INPUT refers to a signal width a pulse with PW1 before thedelay occurs.

When the input signal INPUT is as shown in FIG. 18a, the first switchingsignal SWC1 is in low level and the second switching signal SWC2 is inhigh level, the voltage VCC is only delayed by the second and third PMOStransistor DP2 and DP3 because the fourth PMOS transistor SP1 is turnedon while the fifth PMOS transistor SP2 is turned off. The pulse widthPW1 as shown in FIG. 18c is thus obtained.

If either the fourth PMOS transistor SP1 or the fifth PMOS transistorSP2 is turned on, the voltage VCC is delayed by two PMOS transistorsonly. Accordingly, the pulse width PW1 as shown FIG. 18c, which isgreater than that of FIG. 18b, is obtained.

When the input signal INPUT is as shown in FIG. 18a, and the first andsecond switching signals SWC1 and SWC2 are all in high level, thevoltage VCC is delayed by the first to third PMOS transistor DP1 to DP3because the fourth and fifth PMOS transistors SP1 and SP2 are turnedoff. Thus, pulse width PW1 as shown in FIG. 18d, which is greater thanthat of FIG. 18c, is obtained.

Also, as shown in FIGS. 11 and 18, NM1 has a relatively large size sodelay factors do not occur and pulses are generated simultaneously. Thedelay operation is only implemented by DP1, DP2, DP3, SP1, and SP2.,which have relatively great delay factors. Also, the delay is realizedat the end of the pulse because the pulses are generated at the samepoint.

INPUT(pre-PW1) refers to a pulse generated in period E and is generatedthrough a separate circuit different than the circuit generating the W/Lpulse in period B.

The method for detecting the aforementioned nonvolatile ferroelectricmemory device will now be described.

FIG. 14 is a graph showing dependency of memory charges according to thesize of the pulse width PW1, FIGS. 15(a)-15(c) show various examples ofthe pulse width PW1, and FIG. 16 shows dependency of a voltage inducedto a bitline B/L according to variation of the pulse width PW1 in FIGS.15(a)-15(c).

In the present invention, to ensure reliability of the nonvolatilememory chip, a weak cell is removed in advance.

A nonvolatile ferroelectric memory cell driver includes a sensingamplifier S/A arranged between adjacent top and bottom sub cell arrayssub_T and sub_B to sense the top and bottom sub cell arrays, and awordline driver 57 for driving the wordlines of the top and bottom subcell arrays. The method for detecting a weak cell using theaforementioned nonvolatile ferroelectric memory cell driver includes thesteps of selectively outputting a wordline decoding signal from theX-decoder to the wordline driver 57, varying a width of the restorepulse PW1 and outputting the varied width to the wordline driver 57 todetect the weak cell of the top and bottom cell arrays, controlling data(charge amount) to be stored in a memory cell of each cell arraysimultaneously with the output of the restore pulse PW1, varying bitlinesensing levels corresponding to the controlled data, and sensing data ofa memory cell of each cell array to detect a memory cell first reached aminimum sensing level among the varied bitline sensing levels, therebydetermining a weak cell.

In other words, the restore pulse width is varied during readingoperation of the memory cell, so that charge amount (data value) storedin the ferroelectric capacitor of the memory cell is controlled. Thebitline sensing levels are varied to correspond to the controlled chargeamount (data value). A memory cell having a bitline voltage less than aminimum sensing level, which is the voltage on the reference bitlinefrom the reference cell, is determined as a weak cell and theneliminated.

The weak cell detection is implemented for all cells by sequentiallyinputting address signals through a wordline driver. If the bitlinesensing level output through the sensing amplifier S/A is less than aminimum sensing level, a weak cell is detected.

The minimum sensing level corresponds to the minimum voltage foroperating the sensing amplifier S/A. For example, supposing that ΔV2 inFIG. 16 is a sensing level, ΔV2 is compared with the reference level, asshown on FIG. 16. Then, a memory cell showing ΔV1 which is less than ΔV2is determined to be a weak memory, cell, and a cell showing ΔV3 isdetermined to be a normal cell.

FIG. 14 shows dependancy of charges according to the size of the pulsewidth PW1 in the read and write modes of the nonvoatile ferroelectricmemory cell. Referring to FIG. 14, charges of the data having a logicvalue “1” are varied in such a way as Q1<Q2<Q3 when the size of therestore pulse PW1 is P1<P2<P3. At this time, P1, P2 and P3 arecontrolled by the first and second switching signal generators 52 and 53and the pulse width variable controller 55.

FIGS. 15(a)-15(c) and 16 show variation of the pulse width PW1 andvariation of a voltage induced in the bitline B/L during the read mode.Referring to FIGS. 15(a)-15(c) and 16, if the pulse width PW1 is variedin such a way as P1<P2<P3, the data stored in the cell are also varied.Accordingly, the bitline level is varied in such a way as V1<V2<V3.

As described above, the restore pulse width PW1 is varied to control thedata stored in the cell, so that the bitline sensing level is varied.Thus, if a voltage less than a reference bitline voltage is sensed, thecell is determined as a weak cell.

At this time, the restore pulse PW1 may optionally be varied by a user.

In other words, the pulse width PW1 is varied depending on the switchingsignals SWC1 and SWC2 output from the first and second switching signalgenerators 52 and 53. The varied pulse width is output to each cellarray through the wordline driver 57, so that the data stored in eachcell is controlled. After the bitline sensing level is determined by thesensing amplifier S/A, a cell having a bitline voltage less than thereference bitline voltage is detected as a weak cell and theneliminated.

As aforementioned, the nonvolatile ferroelectric memory device andmethod for detecting a weak cell using the same according to the presentinvention has the following advantages.

First, since the power source voltage detecting circuit (first andsecond switching signal generators) is provided, the weak cell can bedetermined and eliminated without a separate test mode. In addition,since the size of the restore pulse is varied to control the data storedin the memory cell, the weak cell can easily be determined andeliminated even if the process conditions are varied.

The invention being thus described, it will be obvious that the same maybe varied in many ways. Such variations are not to be regarded as adeparture from the spirit and scope of the invention, and all suchmodifications as would be obvious to one skilled in the art are intendedto be included within the scope of the following claims.

What is claimed is:
 1. A nonvolatile ferroelectric memory device,comprising: a nonvolatile ferroelectric memory cell driver including atop cell array and a bottom cell array, a sensing amplifier formedbetween the top and bottom cell arrays, for sensing the top and bottomcell arrays, and a wordline driver for driving a wordline of the top andbottom cell arrays; an X-decoder for selectively outputting a wordlinedecoding signal to the wordline driver; and a pulse width generatingunit for varying a width of a restore pulse and outputting the variedwidth to the wordline driver to detect a weak cell of the top and bottomcell arrays.
 2. The nonvolatile ferroelectric memory device of claim 1,wherein the top and bottom cell arrays include a reference cell providedin one bitline and a plurality of main cells driven by a bitline signalequal to the reference cell.
 3. The nonvolatile ferroelectric memorydevice of claim 1, wherein the pulse width generating unit includesfirst and second switching signal generators for outputting switchingcontrol signals to vary the restore pulse width, and a pulse widthvariable controller for selectively receiving the switching controlsignals of the first and second switching signal generators to vary therestore pulse.
 4. The nonvolatile ferrolectric memory device of claim 3,wherein the first switching signal generator includes: a system powervoltage sensitive divider for descending system power at a constantratio to output a power voltage variation through a first node; a signalsynchronizing unit for synchronizing an output variation of the systempower voltage sensitive divider with an external chip enable signal; alevel maintaining unit for maintaining a relatively high level statewhen a second node of a transistor switched by the first node is in arelatively high level; a current supplying unit for supplying current tothe second node to maintain the second node at a relatively high levelin a normal voltage state; a control unit for controlling the currentsupplying unit in response to the second node and the external chipenable signal; and a high voltage determining unit for detecting a levelof the second node to determine a relatively high voltage and a normalvoltage.
 5. The nonvolatile ferroelectric memory device of claim 4,wherein the system power voltage sensitive divider includes a pluralityof NMOS transistors connected in series, a drain terminal of the firstNMOS transistor being connected to a power source voltage terminal, anda power source voltage being applied to each gate of the NMOStransistors.
 6. The nonvolatile ferroelectric memory device of claim 4,wherein the signal synchronizing unit receives a chip enable signal andan output signal of the high voltage determining unit, and thesynchronizing unit includes two NMOS transistors connected in parallelbetween the system power voltage sensitive divider and a ground voltageterminal.
 7. The nonvolatile ferroelectric memory device of claim 4,wherein the level maintaining unit includes a PMOS transistor formedbetween a power source voltage terminal and the second node, and aninverter for inverting a signal of the second node and inputting it tothe PMOS transistor.
 8. The nonvolatile ferroelectric memory device ofclaim 4, wherein the current supplying units includes a PMOS transistorconnected between a power source voltage terminal and the second nodeand switched under the control of the control unit.
 9. The nonvolatileferroelectric memory device of claim 4, wherein the control unitincludes an inverter for inverting a signal of the second node, and aNAND gate for performing logic AND operation of the chip enable signaland the signal of the inverter and inverting the resultant value. 10.The nonvolatile ferroelectric memory device of claim 4, wherein the highvoltage determining unit includes two inverters connected in series todelay the signal of the second node.
 11. The nonvolatile ferroelectricmemory device of claim 3, wherein the second switching signal generatorincludes: a system power voltage sensitive divider for descending systempower at a constant ratio greater than the system power of the firstswitching signal generator to output a power voltage variation through afirst node; a signal synchronizing unit for synchronizing an outputvariation of the system power voltage sensitive divider with theexternal chip enable signal; a level maintaining unit for maintaining arelatively high level state when a second node of a transistor switchedby the first node is in a relatively high level; a current supplyingunit for supplying current to the second node to maintain the secondnode at relatively high level in a normal voltage state; a control unitfor controlling the current supplying unit in response to the secondnode and the external chip enable signal; and a high voltage determiningunit for detecting a level of the second node to determine a relativelyhigh voltage and a normal voltage.
 12. The nonvolatile ferroelectricmemory device of claim 11, wherein the system power voltage sensitivedivider includes a plurality of NMOS transistors, a drain terminal ofthe first NMOS transistor being connected to a power source voltageterminal, and the first and second NMOS transistors being connected toeach other in series by a diode.
 13. The nonvolatile ferroelectricmemory device of claim 3, wherein the pulse width variable controllerincludes first, second and third PMOS transistors DP1, DP2 and DP3 and afirst NMOS transistor NM1 to which an input signal INPUT for delay iscommonly input, and the first, second and third PMOS transistors DP1,DP2 and DP3 and the first NMOS transistor NM1 being in parallelconnected between a power source voltage terminal and a ground voltageterminal; fourth and fifth PMOS transistors SP1 and SP2 respectivelyconnected with the first PMOS transistor DP1 and the second PMOStransistor DP2 in parallel and driven by first and second switchingsignals SWC1 and SWC2 for varying the pulse width; and an inverter forinverting a signal of a common node of the third PMOS transistor DP3 andthe first NMOS transistor NM1 to output the restore pulse PW1.
 14. Amethod for detecting a weak cell using a nonvolatile ferroelectricmemory device having a nonvolatile ferroelectric memory cell driverincluding a top cell array and a bottom cell array, a sensing amplifierfor sensing the top and bottom cell arrays, and a wordline driver fordriving a wordline of the top and bottom cell arrays, the methodcomprising the steps of: selectively outputting a wordline decodingsignal to the wordline driver; varying a width of a restore pulse;outputting the restore pulse having a varied width to the wordlinedriver to detect a weak cell of the upper and lower cell arrays;controlling data in the form of a charge amount to be stored in a memorycell of each cell array to correspond to the size of the output restorepulse; outputting bitline sensing levels varied to correspond to thesize of the restore pulse; and sensing a memory cell that first reachesa minimum sensing level among the varied bitline sensing levels todetermine a weak cell.
 15. The method of claim 14, wherein the step ofvarying the restore pulse includes the steps of outputting first andsecond switching control signals for varying the width of the restorepulse; and varying the width of the restore pulse in response to thefirst and second switching control signals.
 16. The method of claim 15,wherein the data stored in the memory cell and controlled to correspondto the restore pulse is varied in such that a first charge amount<asecond charge amount<a third charge amount when the restore pulse isvaried such that a first restore pulse<a second restore pulse<a thirdrestore pulse.
 17. The method of claim 16, wherein the bitline sensinglevels varied to correspond to the size of the restore pulse are variedsuch that a first voltage<a second voltage<a third voltage when therestore pulse is varied such that a first pulse<a second pulse<a thirdpulse.
 18. The method of claim 15, wherein the restore pulse includes afirst pulse delayed equivalent to a first turn-on time of one PMOStransistor when the first and second switching control signals are allin a relatively low level, a second pulse delayed equivalent to a secondturn-on time of two PMOS transistors when either the first switchingcontrol signal or the second switching control signal is in a relativelyhigh level, or a third pulse delayed equivalent to a third turn-on timeof three PMOS transistors when the first and second switching controlsignals are in a relatively high level.